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LCD Driver IC
PT6584
DESCRIPTION
The PT6584 are 1/4 duty LCD display drivers that can directly drive up to 220 segments and can control up to four general-purpose output ports. These products also incorporate a key scan circuit that accepts input from up to 30 keys to reduce printed circuit board wiring.
FEATURES
* Key input function for up to 30 keys (A key scan is performed only when a key is pressed.) * 1/4duty - 1/2bias and 1/4duty - 1/3bias drive schemes can be controlled from serial data (up to 220 segments). * Sleep mode and all segments off functions that are controlled from serial data * Segment output port/general-purpose output port function switching that is controlled from serial data * Serial data I/O supports CCB format communication with the system controller * Direct display of display data without the use of a decoder provides high generality * Independent VLCD for the LCD driver block (VLCD can be set to in the range VDD-0.5 to 6.0V.) * Provision of an on-chip voltage-detection type reset circuit prevents incorrect displays * RES pin provided for forcibly initializing the IC internal circuits * RC oscillator circuit
APPLICATION
* Electronic Equipment with LCD Display
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LCD Driver IC
PT6584
BLOCK DIAGRAM
CO M 4 CO M 3 CO M 2 CO M 1 S 4/P 4 S 3/P 3 S 2/P 2 S 1/P 1 S 53 S5
S hi ft R egi ste r
V LCD V LCD 1 V CLD 2 V SS T E ST OSC Clo ck G e ner ato r Con tro l R egi ste r Co mm on D ri ve r Se gme nt Dr iv er & Latc h
DO
DI CL CE V DD V DE T
CCB Inte rfa ce
K ey B uffer
Ke y S ca n
PT6584 V1.1
-2-
K S6 K S5 K S4 K S3 S 55/K S 2 S 54/K S 1
/RE S
K I5 K I4 K I3 K I2 K I1
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LCD Driver IC
PT6584
PIN CONFIGURATION
QFP
VLCD2 VLCD1 T EST VLCD /RES OSC VSS DO VDD KI5 KI4 KI3 66 CE KI2 65 DI CL 79
78
77
76
75
73
69
68
P1/S1 P2/S2 P3/S3 P4/S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
71
70
67
80
74
72
64 63 62 61 60 59 58 57 56 55 54
KI1 KS6 KS5 KS4 KS3 KS2/S55 KS1/S54 COM4 COM3 COM2 COM1 S53 S52 S51 S50 S49 S48 S47 S46 S45 S44 S43 S42 S41
P T 6584- Q
53 52 51 50 49 48 47 46 45 44 43 42 41
26
27
30
31
32
33
34
36
37
S31
S32
S34
S26
S27
S28
S29
S30
S33
S36
S37
S38
S39
S25
PT6584 V1.1
-3-
S35
S40
40
25
28
29
35
38
39
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LCD Driver IC
PT6584
LQFP
VLCD2 VLCD1 P2/S2 P1/S1 T EST VLCD /RES OSC VSS VDD KS6 61 DO KI5 KI4 KI3 KI2 63 CE KI1 62 DI CL
75
80
74
72
70
65
79
78
77
76
73
69
68
67
66
S3/P3 S4/P4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
71
64
60 59 58 57 56 55 54 53 52
KS5 KS4 KS3 KS2/S55 KS1/S54 COM4 COM3 COM2 COM1 S53 S52 S51 S50 S49 S48 S47 S46 S45 S44 S43
P T 6584- LQ
51 50 49 48 47 46 45 44 43 42 41
21
23
24
26
27
28
29
30
31
33
34
36
37
38
39 S41
S24
S31
S32
S34
S23
S26
S27
S28
S29
S30
S33
S36
S37
S38
S39
S25
PT6584 V1.1
-4-
S35
S40
S42
40
22
25
32
35
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LCD Driver IC
PT6584
INPUT/OUPUT CONFIGURATIONS
The schematic diagrams of the input and output circuits of the logic section are shown below:
INPUT PIN: CL, CE, DI, TEST
VDD
VSS
INPUT PIN: KI1 TO KI5
VLCD VDD
VSS
OUTPUT PIN: DO
VDD
VSS
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LCD Driver IC
PT6584
OUTPUT PIN: S1/P1 TO S4/P4, S5 TO S53, KS1/S54, KS2/S55
VLCD VLCD VLCD1
VSS
VSS
VLCD2
OUTPUT PIN: KS3 TO KS6
VLCD
VSS
OUTPUT PIN: COM1 TO COM3, COM4
VLCD VLCD1
VSS
VLCD2
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LCD Driver IC
PT6584
PIN DESCRIPTION
Pin Name S1/P1 S2/P2 S3/P3 S4/P4 S4 ~ S53 COM1 COM2 COM3 COM4/S74 I/O Active Handling when unused OPEN Description Segment outputs for displaying the display data transferred by serial data input. The S1/P1 to S4/P4 pins can be used as general-purpose output ports under serial data control. Common driver outputs The frame frequency fo is given by: fo = (fOSC/512)Hz. Key scan outputs Although normal key scan timing lines require diodes to be inserted in the timing lines to prevent shorts, since these outputs are unbalanced CMOS transistor outputs, these outputs will not be damaged by shorting when these outputs are used to form a key matrix. The KS1/S54 and KS2/S55 pins can be used as segment outputs when so specified by the control data. Key scan inputs These pins have built-in pull-down resistors. Oscillator connection An oscillator circuit is formed by connecting an external resistor and capacitor at this pin. Serial data interface connections to the controller. Note that DO, being an open-drain output, requires a pull-up resistor. CE: Chip enable CL: Synchronization clock DI: Transfer data DO: Output data Reset signal input /RES=low ---- Display off Key scan disabled All key data is reset to low /RES=high --- Display on Key scan enabled However, serial data can be transferred when /RES is low. This pin must be connected to ground Used for applying the LCD drive 2/3 bias voltage externally. Must be connected to VLCD2 when a 1/2 bias drive scheme is used. Used for applying the LCD drive 1/3 bias voltage externally. Must be connected to VLCD1 when a 1/2 bias drive scheme is used. Logic block power supply connection. Provide a voltage of between 3.3 and 6.0V. LCD driver block power supply connection. Provide a voltage of between VDD-0.5 and 6.0V. Power supply connection. Connect to ground. Pin No. QFP 1 2 3 4 5 ~ 53 54 55 56 57 58 59 60 ~ 63 64 ~ 68 75 78 79 80 77 LQFP 79 80 1 2 3 ~ 51 52 53 54 55 56 57 58 ~ 61 62 ~ 66 73 76 77 78 75
O
-
O
-
OPEN
KS1/S54 KS2/S56 KS3 ~ KS6
O
-
OPEN
KI1 ~ KI5 OSC CE CL DI DO
I I/O I I I O
H H
GND VDD
GND OPEN
/RES
I
L
VDD
76
74
TEST VLCD1 VLCD2 VDD VLCD VSS
I I I -
-
OPEN OPEN -
74 71 72 69 70 73
72 69 70 67 68 71
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LCD Driver IC
PT6584
FUNCTION DESCRIPTION
SERIAL DATA INPUT
When CL is stopped at the low level.
CE
CL
DI
0 B0
1 B1
0 B2
0 B3
0 A0
0 A1
1 A2
0 A3
D1
D2
D3
D 51
D 52
D 53
D 54
D 55
D 56
0
0
0
0
0
S0
S1
K0
K1
P0
P1
P2
SC
DR
0
0
D isp la y D a ta DO
C o nt r o l D at a
DD
CE
CL
DI
0 B0
1 B1
0 B2
0 B3
0 A0
0 A1
1 A2
0 A3
D 57
D 58
D 59
D 10 7 D 10 8 D 10 9 D 110 D 111 D 112
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
D isp la y D a ta DO
F ix ed D a ta
DD
CE
CL
DI
0 B0
1 B1
0 B2
0 B3
0 A0
0 A1
1 A2
0 A3
D 113
D 114 D 115
D 16 3 D 16 4 D 16 5 D 16 6 D 16 7 D 16 8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
D isp la y D a ta DO
F ix ed D a ta
DD
CE
CL
DI
0 B0
1 B1
0 B2
0 B3
0 A0
0 A1
1 A2
0 A3
D 16 9
D 17 0 D 17 1
D 21 9 D 22 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
D isp la y D a ta DO
Fix ed D a ta
DD
Figure 1 Notes: 1. B0 to B3, A0 to A3=CCB address. 2. D=Direction Data.
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LCD Driver IC
When CL is stopped at the high level.
CE
PT6584
CL
DI
0 B0
1 B1
0 B2
0 B3
0 A0
0 A1
1 A2
0 A3
D1
D2
D3
D 51
D 52
D 53
D 54
D 55
D 56
0
0
0
0
0
S0
S1
K0
K1
P0
P1
P2
SC
DR
0
0
D isp la y D a ta DO
C o nt ro l D at a
DD
0 B0
1 B1
0 B2
0 B3
0 A0
0 A1
1 A2
0 A3
D 57
D 58
D 59
D 10 7 D 10 8 D 10 9 D 110 D 111 D 112
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
D isp la y D a ta
Fix ed D a ta
DD
0 B0
1 B1
0 B2
0 B3
0 A0
0 A1
1 A2
0 A3
D 113 D 114 D 115
D 16 3 D 16 4 D 16 5 D 16 6 D 16 7 D 16 8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
D isp la y D a ta
Fix ed D a ta
DD
0 B0
1 B1
0 B2
0 B3
0 A0
0 A1
1 A2
0 A3
D 16 9 D 17 0 D 17 1
D 21 9 D 22 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
D isp la y D a ta
Fix ed D a ta
DD
Figure 2 Notes: 1. B0 to B3, A0 to A3=CCB address. 2. DD=Direction Date. CCB address D1 to D220 S0, S1 K0, K1 P0 to P2 SC DR : 42H : Display data : Sleep control data : Key scan output/segment output selection data : Segment output port/general-purpose output port selection data : Segment on/off control data : 1/2 bias or 1/3 bias drive selection data
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LCD Driver IC
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CONTROL DATA
S0, S1: SLEEP CONTROL DATA
These control data bits switch between normal mode and sleep mode and set the states of the KS1 to KS6 key scan outputs during key scan standby.
Control Data S0 S1 0 0 0 1 1 0 1 1 Mode Normal Sleep Sleep Sleep OSC Oscillator Oscillator operating Stopped Stopped Stopped Segment Outputs Common Outputs Operating L L L Output Pin States During Key Scan Standby KS1 KS2 KS3 KS4 KS5 KS6 H H H H H H L L L L L H L L L L H H H H H H H H
Note: This assumes that the KS1/S54 and KS2/S55 output pins are selected for key scan output.
K0, K1: KEY SCAN OUTPUT/SEGMENT OUTPUT SELECTION DATA
These control data bits switch the functions of the KS1/S54 and KS2/S55 output pins between key scan output and segment output. Control Data K0 K1 0 0 0 1 1 X Output Pin State KS1/S54 KS2/S55 KS1 KS2 S54 KS2 S54 S55 Maximum Number of Input Keys 30 25 20
Notes: 1. X=Don't care 2. KSn (n=1 or 2): Key scan output 3. Sn (n=54 or 55): Segment output
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LCD Driver IC
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P0 TO P2: SEGMENT OUTPUT PORT/GENERAL-PURPOSE OUTPUT PORT SELECTION DATA
These control data bits switch the functions of the S1/P1 to S4/P4 output pins between the segment output port and the general-purpose output port. Control Data P0 P1 P2 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 Notes: 1. Sn (n=1 to 4): Segment output port 2. Pn (n=1 to 4): General-purpose output port The table below lists the correspondence between the display data and the output pins when these pins are selected to be general-purpose output ports. Output Pin S1/P1 S2/P2 S3/P3 S4/P4 Corresponding Display Data D1 D5 D9 D13 Output Pin State S1/P1 S2/P2 S3/P3 S4/P4 S1 S2 S3 S4 P1 S2 S3 S4 P1 P2 S3 S4 P1 P2 P3 S4 P1 P2 P3 P4
For example, if the S4/P4 output pin is selected to be a general-purpose output port, the S4/P4 output pin will output a high level (VLCD) when the display data D13 is 1, and will output a low level (Vss) when D13 is 0.
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LCD Driver IC SC: SEGMENT ON/OFF CONTROL DATA
This control data bit controls the on/off state of the segments. SC 0 1 Display State On Off
PT6584
However, note that when the segments are turned off by setting SC to 1, the segments are turned off by outputting segment off waveforms from the segment output pins.
DR: 1/2 BIAS OR 1/3 BIAS DRIVE SELECTION DATA
This control data bit switches between LCD 1/2 bias or 1/3 bias drive. DR 0 1 Bias Drive Scheme 1/3 bias drive 1/2 bias drive
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LCD Driver IC
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DISPLAY DATA AND OUTPUT PIN CORRESPONDENCE
Output Pin S1/P1 S2/P2 S3/P3 S4/P4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 COM1 D1 D5 D9 D13 D17 D21 D25 D29 D33 D37 D41 D45 D49 D53 D57 D61 D65 D69 D73 D77 D81 D85 D89 D93 D97 D101 D105 D109 COM2 D2 D6 D10 D14 D18 D22 D26 D30 D34 D38 D42 D46 D50 D54 D58 D62 D66 D70 D74 D78 D82 D86 D90 D94 D98 D102 D106 D110 COM3 D3 D7 D11 D15 D19 D23 D27 D31 D35 D39 D43 D47 D51 D55 D59 D63 D67 D71 D75 D79 D83 D87 D91 D95 D99 D103 D107 D111 COM4 D4 D8 D12 D16 D20 D24 D28 D32 D36 D40 D44 D48 D52 D56 D60 D64 D68 D72 D76 D80 D84 D88 D92 D96 D100 D104 D108 D112 Output Pin S29 S30 S31 S32 S33 S34 S35 S36 S37 S38 S39 S40 S41 S42 S43 S44 S45 S46 S47 S48 S49 S50 S51 S52 S53 KS1/S54 KS2/S55 COM1 D113 D117 D121 D125 D129 D133 D137 D141 D145 D149 D153 D157 D161 D165 D169 D173 D177 D181 D185 D189 D193 D197 D201 D205 D209 D213 D217 COM2 D114 D118 D122 D126 D130 D134 D138 D142 D146 D150 D154 D158 D162 D166 D170 D174 D178 D182 D186 D190 D194 D198 D202 D206 D210 D214 D218 COM3 D115 D119 D123 D127 D131 D135 D139 D143 D147 D151 D155 D159 D163 D167 D171 D175 D179 D183 D187 D191 D195 D199 D203 D207 D211 D215 D219 COM4 D116 D120 D124 D128 D132 D136 D140 D144 D148 D152 D156 D160 D164 D168 D172 D176 D180 D184 D188 D192 D196 D200 D204 D208 D212 D216 D220
Note: This is for the case where the output pins S1/P1 to S4/P4, KS1/S54 and KS2/S55 are selected for use as segment outputs.
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LCD Driver IC
For example, the table below lists the segment output states for the S11 output pin. D41 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Display Data D42 D43 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 D44 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Output Pin State (S11)
PT6584
The LCD segment for COM1, COM2, COM3 and COM4 are off. The LCD segment for COM4 is on. The LCD segment for COM3 is on. The LCD segments for COM3 and COM4 are on. The LCD segment for COM2 is on. The LCD segments for COM2 and COM4 are on. The LCD segments for COM2 and COM3 are on. The LCD segments for COM2, COM3 and COM4 are on. The LCD segment for COM1 is on. The LCD segments for COM1 and COM4 are on. The LCD segments for COM1 and COM3 are on. The LCD segments for COM1, COM3 and COM4 are on. The LCD segments for COM1 and COM2 are on. The LCD segments for COM1, COM2 and COM4 are on. The LCD segments for COM1, COM2 and COM3 are on. The LCD segments for COM1, COM2, COM3 and COM4 are on.
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LCD Driver IC
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SERIAL DATA OUTPUT
When CL is stopped at the low level.
CE CL
DI
1 B0
1 B1
0 B2
0 B3
0 A0
0 A1
1 A2
0 A3
DO
X
KD 1
KD 2
KD 27 KD 28 KD 29 KD 30
SA
O u tp u t Da ta
Notes: 1. X=Don't care 2. B0 to B3, A0 to A3: CCB address When CL is stopped at the high level.
CE
CL DI
1 B0
1 B1
0 B2
0 B3
0 A0
0 A1
1 A2
0 A3 X KD 1 KD 2 KD 3 KD 28 KD 29 KD 30 SA X
DO
O u tp u t Da ta
Notes: 1. X=Don't care 2. B0 to B3, A0 to A3: CCB address 3. CCD address: 43H 4. KD1 to KD30: Key data 5. SA: Sleep acknowledge data 6. If a key data read operation is executed when DO is high, the read key data (KD1 to KD30) and sleep acknowledge data (SA) will be invalid.
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LCD Driver IC
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OUTPUT DATA
KD1 TO KD30: KEY DATA
When a key matrix of up to 30 keys is formed from the KS1 to KS6 output pins and the KI1 to KI5 input pins and one of those keys is pressed, the key output data corresponding to that key will be set to 1. The table shows the relationship between those pins and the key data bits. Item KS1/S54 KS2/S55 KS3 KS4 KS5 KS6 KI1 KD1 KD6 KD11 KD16 KD21 KD26 KI2 KD2 KD7 KD12 KD17 KD22 KD27 KI3 KD3 KD8 KD13 KD18 KD23 KD28 KI4 KD4 KD9 KD14 KD19 KD24 KD29 KI5 KD5 KD10 KD15 KD20 KD25 KD30
When the KS1/S54 and KS2/S55 output pins are selected to be segment outputs by control data bits K0 and K1 and a key matrix of up to 20 keys is formed using the KS3 to KS6 output pins and the KI1 to KI5 input pins, the KD1 to KD10 key data bits will be set to 0.
SA: SLEEP ACKNOWLEDGE DATA
This output data is set to the state when the key was pressed. Also, while DO will be low in this case, if serial data is input and the mode is set (to normal or sleep mode) during this period, that mode will be set. SA will be 1 in the sleep mode and 0 in the normal mode.
SLEEP MODE
Sleep mode is set up by setting S0 or S1 in the control data to 1. The segment outputs will all go low and the common outputs will also go low, and the oscillator on the OSC pin will stop (it will be started by a key press). This reduces power dissipation. This mode is cleared by sending control data with both S0 and S1 set to 0. However, note that the S1/P1 to S4/P4 outputs can be used as general -purpose output ports according to the state of the P0 to P2 control data bits, even in sleep mode. (See the control data description for details.)
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KEY SCAN OPERATION FUNCTIONS
KEY SCAN TIMING
The key scan period is 384T(s). To reliably determine the on/off state of the keys, the PT6584 scans the keys twice and determines that a key has been pressed when the key data agrees. It outputs a key data read request (a low level on DO) 800T(s) after starting a key scan. If the key data dose not agree and a key was pressed at that point, it scans the keys again. Thus the PT6584 cannot detect a key press shorter than 800T(s).
KS1 1 2 1 2
KS2
KS3
3
3
KS4

4
4

KS5
5
5
KS5
6 768T [s] T=
6
Key on
1 fosc
Note: *: In sleep mode the high/low state of these pins is determined by the S0 and S1 bits in the control data. Key scan output signals are not output from pins that are set low.
IN NORMAL MODE
* The pins KS1 to KS6 are set high. * When a key is pressed a key scan is started and the keys are scanned until all keys are released. Multiple key presses are recognized by determining whether multiple key data bits are set. 1 * If a key is pressed for longer than 800T(s) (Where T= ) the PT6584 outputs a key data read fosc request (a low level on DO) to the controller. The controller acknowledges this request and reads the key data. However, if CE is high during a serial data transfer, DO will be set high. * After the controller reads the key data, the key data read request is cleared (DO is set high) and the PT6584 performs another key scan. Also note that DO, being an open-drain output, requires a pull-up resistor (between 1 and 10K).
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LCD Driver IC
Key Input 1 Key Input 2 Key scan
80 0T[s] 80 0T[s] 80 0T[s]
PT6584
CE
Se rial da ta tra nsfe r Se rial da ta tra nsfe r Ke y ad dre ss (43 H) Se rial da ta tra nsfe r Ke y ad dre ss Ke y ad dre ss
DI DO
Ke y da ta r ead re que st
Ke y da ta r ead
Ke y da ta r ead Ke y da ta r ead re que st
Ke y da ta r ead Ke y da ta r ead re que st T= 1 fosc
IN SLEEP MODE
* The pins KS1 to KS6 are set to high or low by the S0 and S1 bits in the control data. (See the control data description for details.) * If a key on one of the lines corresponding to a KS1 to KS6 pin which is set high is pressed, the oscillator on the OSC pin is started and a key scan is performed. Keys are scanned until all keys are released. Multiple key presses are recognized by determining whether multiple key data bits are set. 1 * If a key is pressed for longer than 800T(s)(Where T= ) the PT6584 outputs a key data read fosc request (a low level on DO) to the controller. The controller acknowledges this request and reads the key data. However, if CE is high during a serial data transfer, DO will be set high. * After the controller reads the key data, the key data read request is cleared (DO is set high) and the PT6584 performs another key scan. However, this does not clear sleep mode. Also note that DO, being an open-drain output, requires a pull-up resistor (between 1 and 10K). * Sleep mode key scan example
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LCD Driver IC
Example: S0=0, S1=1 (sleep with only KS6 high)
(L) KS 1 (L) KS 2 (L) KS 3 (L) KS 4 (L) KS 5 (H ) KS6 KI 1 KI 2 KI 3 KI 4 KI 5 W h e n a n y o n e o f th e se ke y s i s p r e s s e d , th e o s ci l la to r o n th e O S C p i n is s ta r te d a n d th e k e y s a r e s ca n n e d .
PT6584
Note: *: These diodes are required to reliable recognize multiple key presses on the KS6 line when sleep mode state with only KS6 high, as in the above example. That is, these diodes prevent incorrect operations due to sneak currents in the KS6 key scan output signal when keys on the KS1 to KS5 lines are pressed at the same time.
Key Input (KS6 line) Key scan
80 0T[s] 80 0T[s]
CE
Se rial da ta tran sfe r Se rial da ta tran sfe r Ke y ad dre ss (43 H) Se rial da ta tran sfe r Ke y ad dre ss
DI DO
Ke y da ta r ead Ke y da ta r ead re que st Ke y da ta r ead Ke y da ta r ead re que st T= 1 fosc
MULTIPLE KEY PRESSES
Although the PT6584 is capable of key scanning without inserting diodes for dual key presses, triple key presses on the KI1 to KI5 input pin lines, or multiple key presses on the KS1 to KS6 output pin lines, multiple presses other than these cases may result in keys that were not pressed recognized as having been pressed. Therefore, a diode must be inserted in series with each key. Applications that do not recognize multiple key presses of three or more keys should check the key data for three or more 1 bits and ignore such data.
PT6584 V1.1 - 19 August, 2006
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LCD Driver IC
PT6584
1/4 DUTY, 1/2 BIAS DRIVE TECHNIQUE
fosc/512 [Hz]
C OM1
V L CD V L CD 1, V L CD2 0V V L CD V L CD 1, V L CD2 0V V L CD V L CD 1, V L CD2 0V V L CD V L CD 1, V L CD2 0V V L CD V L CD 1, V L CD2 0V V L CD V L CD 1, V L CD2 0V V L CD V L CD 1, V L CD2 0V V L CD V L CD 1, V L CD2 0V V L CD V L CD 1, V L CD2 0V V L CD V L CD 1, V L CD2 0V V L CD V L CD 1, V L CD2 0V V L CD V L CD 1, V L CD2 0V V L CD V L CD 1, V L CD2 0V V L CD V L CD 1, V L CD2 0V V L CD V L CD 1, V L CD2 0V
C OM2
C OM3
C OM4
LC D dri ver out put w hen al l LCD s egmen ts co rres pondi ng to C OM 1, COM 2, C O M3 an d COM4 are turn ed off) LC D dri ver out put w hen onl y LC D s egmen ts co rres pondi ng to C OM1 are on . LC D dri ver out put w hen onl y LC D s egmen ts co rres pondi ng to C OM2 are on . LC D dri ver out put w hen LC D s egme nts c orres pondi ng to COM 1 and CO M 2 are on . LC D dri ver out put w hen onl y LC D s egmen ts co rres pondi ng to C OM3 are on . LC D dri ver out put w hen LC D s egme nts c orres pondi ng to COM 1 and CO M 3 are on. LC D dri ver out put w hen LC D s egme nts c orres pondi ng to COM 2 and CO M 3 are on . LC D dri ver out put w hen LC D s egme nts c orres pondi ng to COM 1, C O M2 and C O M3 are on . LC D dri ver out put w hen onl y LC D s egmen ts co rres pondi ng to C OM4 are on . LC D dri ver out put w hen LC D s egme nts c orres pondi ng to COM 2 and CO M 4 are on . LC D dri ver out put w hen al l LCD seg ment s c orres pondi ng to COM 1, C O M2, COM 3 and C O M4 are o n.
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LCD Driver IC
PT6584
1/4 DUTY, 1/3 BIAS DRIVE TECHNIQUE
fosc/512[Hz]
V L CD V L CD 1 V L CD 2 0V V L CD V L CD 1 V L CD 2 0V V L CD V L CD 1 V L CD 2 0V V L CD V L CD 1 V L CD 2 0V V L CD V L CD 1 V L CD 2 0V V L CD V L CD 1 V L CD 2 0V V L CD V L CD 1 V L CD 2 0V V L CD V L CD 1 V L CD 2 0V V L CD V L CD 1 V L CD 2 0V V L CD V L CD 1 V L CD 2 0V V L CD V L CD 1 V L CD 2 0V V L CD V L CD 1 V L CD 2 0V V L CD V L CD 1 V L CD 2 0V V L CD V L CD 1 V L CD 2 0V V L CD V L CD 1 V L CD 2 0V
C OM1
C OM2
C OM3
C OM4
LC D dri ver output w hen al l LCD seg ment s c orres pondi ng t o CO M1 ,C OM2, C O M3 and C O M4 are tur ned off)
LC D dri ver output w hen onl y LC D s egmen ts c orres pondi ng t o CO M1 a re on.
LC D dri ver output w hen onl y LC D s egmen ts c orres pondi ng t o CO M2 a re on.
LC D dri ver output w hen LC D s egmen ts c orres pondi ng t o CO M1 , C OM2 are o n.
LC D dri ver output w hen onl y LC D s egmen ts c orres pondi ng t o CO M3 a re on.
LC D dri ver output w hen LC D s egmen ts c orres pondi ng t o CO M1 a nd COM 3 are on.
LC D dri ver output w hen LC D s egmen ts c orres pondi ng t o CO M2 a nd COM 3 are on . LC D dri ver output w hen LC D s egmen ts c orres pondi ng t o CO M1 , C OM2 and C O M3 are on . LC D dri ver output w hen onl y LC D s egmen ts c orres pondi ng t o CO M4 a re on.
LC D dri ver output w hen LC D s egmen ts c orres pondi ng t o CO M2 a nd COM 4 are on . LC D dri ver output w hen LC D s egmen ts c orres pondi ng t o CO M1 , C OM2, COM 3 and C O M4 are on .
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LCD Driver IC
PT6584
VOLTAGE DETECTION TYPE RESET CIRCUIT (VDET)
This circuit generates an output signal and resets the system when logic block power is first applied and when the voltage drops, i.e., when the logic block power supply voltage is less than or equal to the power down detection voltage VDET, which is 3.0V, typical. To assure that this function operates reliably, a capacitor must be added to the logic block power supply line so that the logic block power supply voltage VDD rise time when the logic block power is first applied and the logic block power supply voltage VDD fall time when the voltage drops are both at least 1ms. (see Figure 3)
POWER SUPPLY SEQUENCE
The following sequences must be observed when power is turned on and off. (see Figure 3 and 4.) * Power on: Logic block power supply(VDD) on LCD driver block power supply(VLCD) on. * Power off: LCD driver block power supply(VLCD) off Logic block power supply(VDD) off. However, if the logic and LCD driver block use a shared power supply, then the power supplies can be turned on and off at the same time.
SYSTEM RESET
The PT6584 supports the reset methods described below. When a system reset is applied, display is turned off, key scanning is stopped, and all the key data is reset to low. When the reset is cleared, display is turned on and key scanning become possible.
RESET METHODS
(1) Reset at power-on and power-down If at least 1ms is assured as the logic block supply voltage VDD rise time when logic block power is applied, a system reset will be applied by the VDET output signal when the logic block supply voltage is brought up. If at least 1 ms is assured as the logic block supply voltage VDD fall time when logic block power drops, a system reset will be applied in the same manner by the VDET output signal when the supply voltage is lowered. Note that the reset is cleared at the point when all the serial data (the display data D1 to D220 and the control data) has been transferred, i.e., on the fall of the CE signal on the transfer of the last direction data, after all the direction data has been transferred. However, the above operations will be performed regardless of the state (high or low) of the /RES pin. If RES is high, the reset will be cleared at the point the above operations are completed. On the other hand, if /RES is low, the system will remain in the reset period as long as /RES is not set high, even if the above operations are completed. (See Figure 3) (2) Reset when the logic block power supply voltage is in the allowable operating range (VDD=3.3 to 6.0V). The system is reset when the /RES pin is set low, and the reset is cleared by setting /RES pin high.
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LCD Driver IC
t1 t2
PT6584
t3 t4
V DD
V DE T
V DE T
V LC D
CE D1 to D56 S0 , S 1, K0 , K 1 P0 to P 2, SC , D R
Di sp l a y a n d co n tr o l d a ta tr a n sfe r Un d e fi n ed
V IL
Inte rn al data
De fi n e d
Un d e fi n ed
Inte rn al da ta ( D5 7 to D11 2)
Un d e fi n ed
De fi n e d
Un d e fi n ed
In ter nal d ata (D 113 to D 168 )
Un d e fi n ed
De fi n e d
Un d e fi n ed
Inte rn al data ( D1 69 to D22 0)
Un d e fi n ed S ys te m r e se t p e r io d t1 t2 t3 t4

De fi n e d
Un d e fi n ed
1 [m s] ( L o gi c bl o ck po w e r s u pp l y v ol ta g e V DD r i se ti me ) 0 0 1 [m s] ( L o gi c bl o ck po w e r s u pp l y v ol ta g e V DD fa l l ti me )
Figure 3
PT6584 INTERNAL BLOCK STATES DURING THE RESET PERIOD
* CLOCK GENERATOR Reset is applied and the base clock is stopped. However, the OSC pin state (normal or sleep mode) is determined after the S0 and S1 control data bits are transferred. * COMMON DRIVER, SEGMENT DRIVER & LATCH Reset is applied and the display is turned off. However, display data can be input to the latch circuit in this state. * KEY SCAN Reset is applied, the circuit is set to the initial state, and at the same time the key scan operation is disabled. * KEY BUFFER Reset is applied and all the key data is set to low. * CCB INTERFACE, CONTROL REGISTER, SHIFT REGISTER Since serial data transfer is possible, these circuits are not reset.
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LCD Driver IC
CO M 4 CO M 3 CO M 2 CO M 1 S 4/P 4 S 3/P 3 S 2/P 2 S 1/P 1 S 53 S5
PT6584
V LCD V LCD 1 V CLD 2 V SS T E ST OSC Clo ck G e ner ato r Con tro l R egi ste r Co mm on D ri ve r S hi ft R egi ste r Se gme nt Dr iv er & Latc h
DO
DI CL CE V DD V DE T
CCB Inte rfa ce
K ey B uffer
Ke y S ca n
Block that are reset
PT6584 V1.1
- 24 -
K S6 K S5 K S4 K S3 S 55/K S 2 S 54/K S 1
/RE S
K I5 K I4 K I3 K I2 K I1
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LCD Driver IC OUTPUT PIN STATES DURING THE RESET PERIOD
Output Pin S1/P1 to S4/P4 S5 to S53 COM1 to COM4 KS1/S54. KS2/S55 KS3 to KS5 KS6 DO State during Reset L (Note 2) L L L (Note 2) X (Note 3) H H (Note 4)
PT6584
Notes: 1. X=Don't care 2. These output pins are forcibly set to the segment output function and held low. 3. When power is first applied, these output pins are undefined until the S0 and S1 control data bits have been transferred. 4. Since this output pin is an open-drain output, a pull-up resistor of between 1 and 10K is required. This pin remains high during the reset period even if a key data read operation is performed.
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LCD Driver IC
PT6584
NOTE ON THE CONTROLLER KEY DATA READ TECHNIQUES
TIMER BASED KEY DATA ACQUISITION
* Flowchart
CE=L
DO=L
NO
YES Key data read processing
* Timing Chart
Key on Key Input Key S can t5 CE DI DO
Ke y d ata r ea d r equ est
Key on
t6 t8
t7 t7
t5 t8
t7
t5 t8
Ke y d ata r ea d
t9
Co ntrolle r d ete rmina tion (key on ) Co ntr olle r d ete r mina tion ( key on )
t9
Co ntrolle r d ete rmina tion (key off )
t9
t9
Co ntrolle r d ete rmina tion (key on ) Co ntr olle r d ete r mina tion ( key off )
t5 t6 t7 t8
: Key scan execution time when the key data agreed for two key scans. (800T(s)) : Key scan execution time when the key data did not agree for two key scans and the key scan was executed again. (1600T(s)) 1 : Key address (43H) transfer time T = fosc : Key data read time
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LCD Driver IC
PT6584
* Explanation In this technique, the controller uses a timer to determine key on/off states and read the key data. The controller must check the DO state when CE is low every t9 period without fail. If DO is low, the controller recognizes that a key has been pressed and executes the key data read operation. The period t9 in this technique must satisfy the following condition. t9>t6+t7+t8 If a key data read operation is executed when DO is high, the read key data (KD1 to KD30) and sleep acknowledge data (SA) will be invalid.
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LCD Driver IC INTERRUPT BASED KEY DATA ACQUISITION
* FLOWCHART
PT6584
CE= L
DO=L YE S K ey data read processing
NO
Wait for at least t10
CE= L
NO
DO=H YE S K ey off
* Timing Chart
Key Input Key S can
Key on
Key on
t5 CE t8 DI
t7
Ke y a ddr ess Ke y d ata rea d
t5 t8
t7
t6 t8
t7
t5 t8
t7
DO
Ke y d ata rea d requ est
t10
Co ntr o ller de ter m inat ion (key off ) Co ntr o ller de ter m inat ion (key on )
t10
Co ntr o ller de ter m inat ion (key on )
t10
Co ntr o ller de ter m inat ion (key on )
t10
Co ntr o ller de ter m inat ion (key off )
Co ntro ller de ter m inat ion ( key on )
t5 t6 t7 t8
: Key scan execution time when the key data agreed for two key scans. (800T(s)) : Key scan execution time when the key data did not agree for two key scans and the key scan was executed again. (1600T(s)) 1 : Key address (43H) transfer time T = fosc : Key data read time
- 28 August, 2006
PT6584 V1.1
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LCD Driver IC
PT6584
* Explanation In this technique, the controller uses interrupts to determine key on/off states and read the key data. The controller must check the DO state when CE is low. If DO is low, the controller recognizes that a key has been pressed and executes the key data read operation. After that the next key on/off determination is performed after the time t10 has elapsed by checking the DO state when CE is low and reading the key data. The period t10 in this technique must satisfy the following condition. t10 > t6 If a key data read operation is executed when DO is high, the read key data (KD1 to KD30) and sleep acknowledge data (SA) will be invalid.
NOTE ON TRANSFERRING DISPLAY DATA FROM THE CONTROLLER
The display data (D1 to D220) is transferred to the PT6584 in four operations. All of the display data should be transferred within 30ms to maintain the quality of the displayed image.
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LCD Driver IC
PT6584
ABSOLUTE MAXIMUM RATINGS
(VSS=0V, Ta=25) Parameter Maximum supply voltage Input voltage Symbol VDD max VLCD max VIN1 VIN2 VIN3 VOUT1 VOUT2 VOUT3 IOUT1 IOUT2 IOUT3 IOUT4 Pd max Topr Tstg Condition VDD VLCD CE, CL, DI, /RES OSC, TEST VLCD1, VLCD2, KI1 to KI5 DO OSC S1 to S55, COM1 to COM4, KS1 to KS6, P1 to P4 S1 to S55 COM1 to COM4 KS1 to KS6 P1 to P4 Ta = 85 Rating -0.3 ~ +7.0 -0.3 ~ +7.0 -0.3 ~ VDD+0.3 -0.3 ~ VDD+0.3 -0.3 ~ VLCD+0.3 -0.3 ~ VDD+0.3 -0.3 ~ VDD+0.3 -0.3 ~ VLCD+0.3 300 3 1 5 200 -40 ~ +85 -65 ~ +150 A mA mW Unit V V
Output voltage
V
Output current Allowable power dissipation Operating temperature Storage temperature
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LCD Driver IC
PT6584
ALLOWABLE OPERATING RANGES
(Ta=-40 to +85, VSS=0V)
Parameter Supply voltage Input voltage Input high level voltage Input low level voltage Recommended external resistance Recommended external capacitance Guaranteed oscillator range Data setup time Data hold time CE wait time CE setup time CE hold time High level clock pulse width Low level clock pulse width Rise time Fall time DO output delay time DO rise time Symbol VDD VLCD VLCD1 VLCD2 VIH1 VIH2 VIL ROSC COSC fosc tds tdh tcp tcs tch tH tL tr tf tdc tdr Condition VDD VLCD VLCD1 VLCD2 CE, CL, DI, /RES KI1 to KI5 CE, CL, DI, /RES, KI1 to KI5 OSC OSC OSC CL,DI: Figure 4 CL, DI: Figure 4 CE, CL: Figure 4 CE, CL: Figure 4 CE, CL: Figure 4 CL: Figure 4 CL: Figure 4 CE, CL, DI: Figure 4 CE, CL, DI: Figure 4 DO, RPU=4.7K, CL=10pf (see note): Figure 4 DO, RPU=4.7K, CL=10pf (see note): Figure 4 Min 3.3 VDD-0.5 0.8 VDD 0.6 VDD 0 25 160 160 160 160 160 160 160 Typ 2/3VLCD 1/3VLCD 43 680 50 160 160 Max 6.0 6.0 VLCD VLCD 6.0 VLCD 0.2 VDD 100 1.5 1.5 Unit V V V V V V V K pF MHz ns ns ns ns ns ns ns ns ns s s
Note: Since DO is an open-drain output, these values depend on the resistance of the pull-up resistor RPU and the load capacitance CL.
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LCD Driver IC
PT6584
ELECTRICAL CHARACTERISTICS
(Ta=-40 to +85, VSS=0V)
Parameter Hysteresis Power-down Detection Voltage Input High level Current Input Low Level Current Input Floating Voltage Pull-down Resistance Output Off Leakage Current Output High Level Voltage Symbol VH VDET IIH IIL VIF RPD IOFFH VOH1 VOH2 VOH3 VOH4 VOL1 VOL2 VOL3 VOL4 VOL5 VMID1 Output Middle Level Voltage (see note) VMID2 VMID3 VMID4 VMID4 Oscillator Frequency fosc IDD1 IDD2 Current Drain ILCD1 ILCD2 ILCD3 CE, CL, DI, /RES: VI=6.0V CE, CL, DI, /RES: VI=0V KI1 to KI5 KI1 to KI5: VDD=5.0V DO: VO=6.0V KS1 to KS6: IO=-500A P1 to P4: IO=-1mA S1 to S55: IO=-20A COM1 to COM4: IO=-100A KS1 to KS6: IO=25A P1 to P4: IO=1mA S1 to S55: IO=20A COM1 to COM4: IO=100A DO: IO=1mA COM1 to COM4: 1/2 bias, IO=100A S1 to S55: 1/3 bias, IO=20A S1 to S55: 1/3 bias, IO=20A COM1 to COM4: 1/3 bias, IO=100A COM1 to COM4: 1/3 bias, IO=100A OSC: Rosc=43K, Cosc=680pF VDD: Sleep mode VDD: VDD=6.0V. output open, fosc=50KHz VLCD: Sleep mode VLCD: VLCD=6.0V, output open, 1/2 bias, fosc=50KHz VLCD: VLCD=6.0V, output open, 1/3 bias, fosc=50KHz Conditions CE, CL, DI, /RES, KI1 to KI5 Min. 1.8 -5.0 50 VLCD-1.0 VLCD-1.0 VLCD-1.0 VLCD-1.0 0.2 1/2VLCD-1.0 2/3VLCD-1.0 1/3VLCD-1.0 2/3VLCD-1.0 1/3VLCD-1.0 40 Typ. 0.1VDD 2.4 100 VLCD-0.5 0.5 0.1 50 270 200 120 Max. 3.2 5.0 0.05VDD 250 6.0 VLCD-0.2 1.5 1.0 1.0 1.0 0.5 1/2VLCD+1.0 2/3VLCD+1.0 1/3VLCD+1.0 2/3VLCD+1.0 1/3VLCD+1.0 60 100 540 5 400 240 A KHz V Unit V V A A V K A V
Output Low Level Voltage
V
Note: Excluding the bias voltage generation divider resistor built into VLCD1 and VLCD2. (See Figure 4.)
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LCD Driver IC
VLCD
PT6584
VLCD1 VLCD2 To the com m on a nd segm en t dr iv er Exc lud in g the se reg is tor s
Figure 4 1. When CL is stopped at the low level
CE
V IH1 50 % V IL V IH1 V IL
VIH 1 VIL tH tr tL tf
CL
tcp tcs
tch
DI
tds DO
tdh D0 tdc D1 tdr
2. When CL is stopped at the high level
V IH 1 t L tr t H tf
CE
V IH1 C L 50 % V IL
V IL
tcp tcs
tch
DI
V IH1 V IL
tds DO
td h D0 tdc D1 tdr
Figure 5
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LCD Driver IC
PT6584
1/2 BIAS APPLICATION CIRCUIT
(FOR NORMAL PANEL USE)
Ke y Ma trix (up t o 3 0 keys)
51 60 59 58 57 56 54 53 52 50 49 48 47 46 44 43 42 S44 55 45 41 S43
S42 40 S41 39 S40 38 S39 37 S38 36 S37 35 S36 34 S35 33 S34 32
COM1
COM4
COM3
KS1/S54
COM2
KS5
KS4
KS3
KS2/S55
S53
S52
S51
S50
S49
S48
S47
S46
61 62 63 64 65 66
KS6 KI1 KI2 KI3 KI4 KI5
*2
+ 5.5 V
68 69
VLC D VLCD 1 VLCD 2
C *1
70
71 VSS 72 73 TEST OSC /RES * 3 DO CE
P T 65 8 4-L Q
S33
31
S32 30 S31 29 S30 28 S29 27 S28 26 S27 25 S26 24 S25 23 S24 22 S23 21
68 0p
43 K MC U V
74
*4
75 76
77 C L 78 79 80 DI P1/S1 P2/S2
S3/P3
S4/P4
S10
10 S12
11 S13
12 S14
13 S15
14 S16
15 S17
16 S18
17 S19
18 S20
19 S21
Notes: 1. C 0.047F 2. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise time when power is applied and the logic block power supply voltage VDD fall time when power drops are both at least 1ms, as the PT6584 is reset by the VDET. 3. If the /RES pin is not used for system reset, it must be connected to the logic block power supply VDD. 4. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10K) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded.
PT6584 V1.1
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20 S22
1
2
3
4
6
7
8
5
9
S11
S5
S6
S7
S8
S9
August, 2006
LCD P anel
+ 5V
67 VD D
S45
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LCD Driver IC
PT6584
1/2 BIAS APPLICATION CIRCUIT
(USE WITH LARGE PANEL)
Ke y Ma trix (up t o 3 0 keys)
51 60 59 58 57 56 54 53 52 50 49 48 47 46 44 43 42 S44 55 45 41 S43
S42 40 S41 39 S40 38 S39 37 S38 36 S37 35 S36 34 S35 33 S34 32
COM1
COM4
COM3
COM2
KS5
KS4
KS3
KS1/S54
S52
S51
61 62 63 64 65 66
KS6 KI1 KI2 KI3 KI4 KI5
+ 5.5 V *1 C R R
*2
68 69 70
VLC D VLCD 1 VLCD 2
71 VSS 72 73 TEST OSC /RES * 3 DO CE
P T 65 8 4-L Q
S33
31
S32 30 S31 29 S30 28 S29 27 S28 26 S27 25 S26 24 S25 23 S24 22 S23 21
68 0p
43 K MC U V
74
*4
75 76
77 C L 78 79 80 DI P1/S1 P2/S2
S3/P3
S4/P4
S10
10 S12
11 S13
12 S14
13 S15
14 S16
15 S17
16 S18
17 S19
18 S20
19 S21
Notes: 1. C 0.047F; 10K R 1K 2. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise time when power is applied and the logic block power supply voltage VDD fall time when power drops are both at least 1ms, as the PT6584 is reset by the VDET. 3. If the /RES pin is not used for system reset, it must be connected to the logic block power supply VDD. 4. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10K) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded.
PT6584 V1.1
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20 S22
1
2
3
4
6
7
8
5
9
S11
S5
S6
S7
S8
S9
August, 2006
LCD P anel
+ 5V
67 VD D
KS2/S55
S45
S53
S50
S49
S48
S47
S46
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LCD Driver IC
PT6584
1/3 BIAS APPLICATION CIRCUIT
(FOR NOEMAL LCD PANEL)
Ke y M atr ix ( up t o 30 keys)
51 60 59 58 57 56 54 53 52 50 49 48 47 46 44 43 42 S44 55 45 41 S43
S42 40 S41 39 S40 38 S39 37 S38 36 S37 35 S36 34 S35 33 S34 32
COM1
COM4
COM3
COM2
KS5
KS4
KS3
KS1/S54
S53
S52
S51
S48
S49
S47
KS2/S55
S46
S50
61 62 63 64 65 66
KS6 KI1 KI2 KI3 KI4 KI5
+ 5.5 V *1 C
*2
68 69 70
VLC D VLCD 1 VLCD 2
C
71 VSS 72 73 TEST OSC /RES * 3 DO CE CL DI P1/S1 P2/S2
P T 6 58 4-L Q
S33
31
S32 30 S31 29 S30 28 S29 27 S28 26 S27 25 S26 24 S25 23 S24 22 S23 21
68 0p
43 K MC U V
74
*4
75 76 77 78 79 80
S3/P3
S4/P4
S10
10 S12
11 S13
12 S14
13 S15
14 S16
15 S17
16 S18
17 S19
18 S20
19 S21
Notes: 1. C 0.047F 2. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise time when power is applied and the logic block power supply voltage VDD fall time when power drops are both at least 1ms, as the PT6584 is reset by the VDET. 3. If the /RES pin is not used for system reset, it must be connected to the logic block power supply VDD. 4. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10K) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded.
PT6584 V1.1
- 36 -
20 S22
1
2
3
4
6
7
8
5
9
S11
S5
S6
S7
S8
S9
August, 2006
LCD P anel
+ 5V
67 VD D
S45
Tel:886-2-66296288 Fax:886-2-29174598 URL:http://www.princeton.com.tw
LCD Driver IC
PT6584
1/3 BIAS APPLICATION CIRCUIT
(USE WITH LARGE PANEL)
Ke y M atrix (up t o 30 keys)
51 60 59 58 57 56 54 53 52 50 49 48 47 46 44 43 42 S44 55 45 41 S43
S42 40 S41 39 S40 38 S39 37 S38 36 S37 35 S36 34 S35 33 S34 32
COM1
COM4
KS1/S54
COM3
COM2
KS5
KS4
KS3
S52
S51
KS2/S55
S53
S49
S48
S47
S46
S50
61 62 63 64 65 66
KS6 KI1 KI2 KI3 KI4 KI5
+ 5.5 V *1 C C R R R
*2
68 69 70
VLC D VLCD 1 VLCD 2
71 VSS 72 73 TEST OSC /RES * 3 DO CE CL DI P1/S1 P2/S2
P T 6 58 4-L Q
S33
31
S32 30 S31 29 S30 28 S29 27 S28 26 S27 25 S26 24 S25 23 S24 22 S23 21
68 0p
43 K MC U V
74
*4
75 76 77 78 79 80
S3/P3
S4/P4
S10
10 S12
11 S13
12 S14
13 S15
14 S16
15 S17
16 S18
17 S19
18 S20
19 S21
Notes: 1. C 0.047F; 10K R 1K 2. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise time when power is applied and the logic block power supply voltage VDD fall time when power drops are both at least 1ms, as the PT6584 is reset by the VDET. 3. If the /RES pin is not used for system reset, it must be connected to the logic block power supply VDD. 4. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10K) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded.
PT6584 V1.1
- 37 -
20 S22
1
2
3
4
6
7
8
5
9
S11
S5
S6
S7
S8
S9
August, 2006
LCD P anel
+ 5V
67 VD D
S45
Tel:886-2-66296288 Fax:886-2-29174598 URL:http://www.princeton.com.tw
LCD Driver IC
PT6584
ORDER INFORMATION
Order Part Number PT6584-Q PT6584-LQ PT6584-Q (L) PT6584-LQ (L) Package Type 80 Pins, QFP 80 Pins, LQFP 80 Pins, QFP 80 Pins, LQFP Top Code PT6584-Q PT6584-LQ PT6584-Q PT6584-LQ
Notes: 1. (L), (C) or (S) = Lead Free. 2. The Lead Free mark is put in front of the data code.
PT6584 V1.1
- 38 -
August, 2006
Tel:886-2-66296288 Fax:886-2-29174598 URL:http://www.princeton.com.tw
LCD Driver IC
PT6584
PACKAGE INFORMATION
80 PINS, QFP (BODY SIZE: 20MM X 14MM, PITCH: 0.80MM)
D D1 -D-
A A2
A1
E1
E
-A-
-B-
L1 e
1
b
c
-C2
SEATING PLANE
R1 -HR2 GAUGE PLANE
0.25mm
S
3
L
PT6584 V1.1
- 39 -
August, 2006
Tel:886-2-66296288 Fax:886-2-29174598 URL:http://www.princeton.com.tw
LCD Driver IC
Symbol A A1 A2 b D D1 E E1 e c c1 L L1 S R1 R2 1 2 3 Min. 0.00 2.50 0.29 Nom. 2.70 23.20 BSC. 20.00 BSC. 17.20 BSC. 14.00 BSC. 0.80 BSC. 0.15 0.88 1.60 BSC. Max. 3.15 0.25 2.90 0.45
PT6584
0.11 0.11 0.73 0.20 0.13 0.13 0o 0o 5
o
0.23 0.19 1.03 0.30 7o 16o 16o
5o
Notes: 1. All dimensioning and tolerancing conform to ASME Y14.5M-1994. 2. Datum Plane H is located at the bottom of the mold parting line coincident with where the lead exits the body. 3. Datums A-B and D to be determined at Datum Plane H. 4. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 do not include mismatch and are determined at the datum plane H. 5. Details of Pin 1 identifier are optional but must be located within the zone indicated. 6. Regardless of the relative size of the upper and lower body sections, Dimensions D1 and E1 are determined at the largest feature of the body exclusive of mold flash and gate burrs, but including any mismatch between the upper and lower section of the molded body. 7. Controlling Dimension: Millimeters 8. Dimension b does not include dambar protrusion. The dambar protrusion(s) shall not cause the lead width to exceed b maximum by more than 0.08 mm. dambar cannot be located on the lower radius or the lead foot. 9. N = No. of leads (N=80) 10. A1 is defined as the distance from the seating plane to the lowest point of the package body. 11. Please refer to JEDEC MS-022 Variation GB-2. JEDEC is the trademark of the JEDEC SOLID STATE TECHNOLOGY ASSOCIATION
PT6584 V1.1 - 40 August, 2006
Tel:886-2-66296288 Fax:886-2-29174598 URL:http://www.princeton.com.tw
LCD Driver IC
PT6584
80 PINS, LQFP (BODY SIZE: 12X12, PITCH: 0.50, THK BODY: 1.40MM)
D D1 -D-
A A2
A1
E1
E
-A-
-B-
L1 e
1
b
c
-C2
SEATING PLANE
R1 -HR2 GAUGE PLANE
0.25mm
S
3
L
PT6584 V1.1
- 41 -
August, 2006
Tel:886-2-66296288 Fax:886-2-29174598 URL:http://www.princeton.com.tw
LCD Driver IC
Symbol A A1 A2 b b1 D D1 e E E1 S R1 R2 L L1 C 1 2 3 Min. 0.05 1.35 0.17 0.17 Nom. 1.40 0.22 0.20 14.00 BSC 12.00 BSC 0.50 BSC 14.00 BSC 12.00 BSC 0.60 1.00 REF 3.5o 12
o
PT6584
Max. 1.60 0.15 1.45 0.27 0.23
0.20 0.08 0.08 0.45 0.09 0o 0o 11
o
0.20 0.75 0.20 7o 13o 13o
11o
12o
Notes: 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. The top package body may be smaller than the bottom package size as much as 0.15mm. 3. Datum A-B and D to be determined at the datum plane H. 4. Dimensions D1 and E1 do not include mold protrusions. Allowable protrusion is 0.25mm per side. d1 and E1 are maximum plastic body size dimensions including mold mismatch. 5. Controlling Dimensions: Millimeters 6. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08mm. Dambar cannot be located on the lower radius or the foot. Minimum space between protrusion and an adjacent lead is 0.07 mm for 0.4mm and 0.5mm pitch package. 7. A1 is defined as the distance from the seating plane to the lowest point on the package body. 8. Refer to JEDEC MS-026 Variation BDD. JEDEC is the trademark of JEDEC SOLID STATE TECHNOLOGY CORPORAITON.
PT6584 V1.1
- 42 -
August, 2006

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